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AT86RF232
initialization vector is zero. However, for non-compliant usage any other initialization
vector can be used. This operation has to be prepared by the microcontroller.
Note:
1. The IEEE 802.15.4-2006 standard MIC algorithm requires CBC mode
encryption only, as it implements a one-way hash function.
11.1.5 Data Transfer – Fast SRAM Access
The ECB and CBC modules including the AES core are clocked with 16MHz. One AES
operation takes t AES = 23.4μs to execute, refer to Table 7-2 . That means that the
processing of the data is usually faster than the transfer of the data via the SPI
interface.
To reduce the overall processing time the Atmel AT86RF232 provides a Fast SRAM
access for the address space 0x82 to 0x94.
Figure 11-5. Packet Structure – Fast SRAM Access Mode.
AES run #0
AES run #n
AES access #0
AES access #1
AES access #n+1
MOSI
cmd add cfg P0 P1
... P14 P15 start
cmd add cfg P0 P1
... P14 P15 start
cmd add cfg xx
xx
...
xx
xx start
MISO
stat xx
xx
xx
xx
...
xx
xx
xx
stat xx
xx
xx C0
... C13 C14 C15
stat xx
xx
xx C0
... C13 C14 C15
Address
0x83
...
0x94
0x83
...
0x94
0x83
...
0x94
byte 0 (cmd)
byte 1 (addr.)
byte 2 (cfg)
byte 3
byte 4
byte 18
byte 19 (start)
MOSI
MISO
SRAM write
PHY_STATUS
address 0x83
XX
<AES_CTRL>
XX
P0[7:0]
XX
P1[7:0]
C0[7:0]
...
...
P15[7:0]
C14[7:0]
<AES_CTRL> (1)
C15[7:0]
Address
0x83
0x84
0x85
0x93
0x94
Note:
1. Byte 19 is the mirrored version of register AES_CTRL on SRAM
address 0x94, see register description AES_CTRL_MIRROR for details.
In contrast to a standard SRAM access, refer to Section 6.2.3 , the Fast SRAM access
allows writing and reading of data simultaneously during one SPI access for
consecutive AES operations ( AES run ).
For each byte P0 transferred to pin 22 (MOSI) for example in “ AES access #1 ” , see
Figure 11-5 (lower part), the previous content of the respective AES register C0 is
clocked out at pin 20 (MISO) with an offset of one byte.
In the example shown in Figure 11-5 the initial plaintext P0 – P15 is written to the
SRAM within
“ AES
access #0 ” .
The last command on address 0x94
(AES_CTRL_MIRROR) starts the AES operation (“ AES run #0 ”) . In the next “ AES
access #1 ” new plaintext data P0 – P15 is written to the SRAM for the second AES run,
in parallel the ciphertext C0 – C15 from the first AES run is clocked out at pin MISO. To
read the ciphertext from the last “ AES run #(n) ” one dummy “ AES access #(n+1) ” is
needed.
Note:
2. The SRAM write access always overwrites the previous processing
result.
129
8321A – MCU Wireless – 10/11
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